The present invention relates to a probe card that collectively inspects a plurality of semiconductor chips in a wafer level and a semiconductor wafer inspection method using the same, and particularly relates to a probe card that performs inspection by transmitting and receiving signals by non-contact coupling, such as inductive coupling or capacitive coupling, and a semiconductor wafer inspection method using the same.
During manufacturing of a semiconductor integrated circuit, a plurality of semiconductor integrated devices (chips) are simultaneously formed through a diffusion process on a semiconductor wafer. However, in the manufacturing process, all the plurality of chips simultaneously manufactured are usually difficult to be made non-defective articles due to various factors, such as dust. Therefore, the manufactured chips need to be individually inspected whether or not the chips are non-defective. The inspection has roughly two sorting processes: inspection for removing defects by actually operating devices and burn in sorting of confirming whether or not the devices have a problem with the reliability also after used in a market for a given period of time.
In order to mount a plurality of chips in one package or to manufacture a device having an increased packaging density by stacking chips in a three dimension manner to connect mutual chips, which is a technique that has been attracting attention in recent years, it is necessary to confirm that each chip is non-defective beforehand. Otherwise, the non-defective ratio of products obtained by integrating a plurality of chips decreases when a larger number of chips are integrated because the total non-defective ratio is determined by the product of the non-defective ratio of each chip.
Therefore, before each chip is mounted, the chips need to be inspected and sorted in a wafer level. As a method therefor, by using a probe card that performs wafer collective contact disclosed in Japanese Patent Publication No. 7-231019 (hereinafter referred to as Document 1) and according to the method disclosed in Japanese Patent Publication No. 8-005666 (hereinafter referred to as Document 2), the probe card is brought into contact with a semiconductor wafer to perform inspection and burn in. The structure of a probe card employing a thin film substrate with a bump that follows changes in the inspection temperature to control the coefficient of thermal expansion to be equal to that of a wafer in the process is also disclosed in Document 1.
In order to obtain electrical connection for each pad electrode of chips, the number of contactable terminals is limited in terms of weight limitation even when the method of Document 2 is used. Therefore, a method for transmitting and receiving signals in a non-contact state using capacitive coupling or inductive coupling that is not limited in the total weight is disclosed in Japanese Patent Publication No. 2009-85720, International Publication No. WO2006/069309 pamphlet, Y. Yoshida, K. Nose, Y. Nakagawa, K. Noguchi, Y. Morita, M. Tago, T. Kuroda, and M. Mizuno, “Wireless DC Voltage Transmission Using Inductive-Coupling Channel for Highly-Parallel Wafer-Level Testing,” IEEE International Solid-State Circuits Conference (ISSCC'09), Dig. Tech. Papers, pp. 470-472, February 2009, and S. Kawai, H. Ishikuro, and T. Kuroda, “A 4.7 Gb/s Inductive Coupling Interposer with Dual Mode Modem,” IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 92-93, June 2009, and the like.